.\" -*- mode: troff; coding: utf-8 -*- .\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp .. .de Vb \" Begin verbatim text .ft CW .nf .ne \\$1 .. .de Ve \" End verbatim text .ft R .fi .. .\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ . ds C` "" . ds C' "" 'br\} .el\{\ . ds C` . ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" .\" If the F register is >0, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .\" .\" Avoid warning from groff about undefined register 'F'. .de IX .. .nr rF 0 .if \n(.g .if rF .nr rF 1 .if (\n(rF:(\n(.g==0)) \{\ . if \nF \{\ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. . if !\nF==2 \{\ . nr % 0 . nr F 2 . \} . \} .\} .rr rF .\" ======================================================================== .\" .IX Title "VERILATOR 1" .TH VERILATOR 1 2024-04-10 "perl v5.38.2" "User Contributed Perl Documentation" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh .SH NAME Verilator \- Translate and simulate SystemVerilog code using C++/SystemC .SH SYNOPSIS .IX Header "SYNOPSIS" .Vb 6 \& verilator \-\-help \& verilator \-\-version \& verilator \-\-binary \-j 0 [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] \& verilator \-\-cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] \& verilator \-\-sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] \& verilator \-\-lint\-only \-Wall [source_files.v]... .Ve .SH DESCRIPTION .IX Header "DESCRIPTION" The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. .PP For documentation see . .SH "ARGUMENT SUMMARY" .IX Header "ARGUMENT SUMMARY" This is a short summary of the arguments to the "verilator" executable. See for the detailed descriptions of these arguments. .PP .Vb 3 \& Verilog package, module, and top module filenames \& Optional C++ files to compile in \& Optional C++ files to link in \& \& +1364\-1995ext+ Use Verilog 1995 with file extension \& +1364\-2001ext+ Use Verilog 2001 with file extension \& +1364\-2005ext+ Use Verilog 2005 with file extension \& +1800\-2005ext+ Use SystemVerilog 2005 with file extension \& +1800\-2009ext+ Use SystemVerilog 2009 with file extension \& +1800\-2012ext+ Use SystemVerilog 2012 with file extension \& +1800\-2017ext+ Use SystemVerilog 2017 with file extension \& +1800\-2023ext+ Use SystemVerilog 2023 with file extension \& \-\-assert Enable all assertions \& \-\-assert\-case Enable unique/unique0/priority case related checks \& \-\-autoflush Flush streams after all $displays \& \-\-bbox\-sys Blackbox unknown $system calls \& \-\-bbox\-unsup Blackbox unsupported language features \& \-\-binary Build model binary \& \-\-build Build model executable/library after Verilation \& \-\-build\-dep\-bin Override build dependency Verilator binary \& \-\-build\-jobs Parallelism for \-\-build \& \-\-cc Create C++ output \& \-CFLAGS C++ compiler arguments for makefile \& \-\-clk Mark specified signal as clock \& \-\-no\-clk Prevent marking specified signal as clock \& \-\-compiler Tune for specified C++ compiler \& \-\-converge\-limit Tune convergence settle time \& \-\-coverage Enable all coverage \& \-\-coverage\-line Enable line coverage \& \-\-coverage\-max\-width Maximum array depth for coverage \& \-\-coverage\-toggle Enable toggle coverage \& \-\-coverage\-underscore Enable coverage of _signals \& \-\-coverage\-user Enable SVL user coverage \& \-D[=] Set preprocessor define \& \-\-debug Enable debugging \& \-\-debug\-check Enable debugging assertions \& \-\-no\-debug\-leak Disable leaking memory in \-\-debug mode \& \-\-debugi Enable debugging at a specified level \& \-\-debugi\- Enable debugging a source file at a level \& \-\-decorations Set output comment and spacing level \& \-\-no\-decoration Disable comments and lower spacing level \& \-\-default\-language Default language to parse \& +define+= Set preprocessor define \& \-\-dpi\-hdr\-only Only produce the DPI header file \& \-\-dump\-defines Show preprocessor defines with \-E \& \-\-dump\-dfg Enable dumping DfgGraphs to .dot files \& \-\-dump\-graph Enable dumping V3Graphs to .dot files \& \-\-dump\-tree Enable dumping Ast .tree files \& \-\-dump\-tree\-addrids Use short identifiers instead of addresses \& \-\-dump\-tree\-dot Enable dumping Ast .tree.dot debug files \& \-\-dump\-tree\-json Enable dumping Ast .tree.json files and .tree.meta.json file \& \-\-dump\- Enable dumping everything in source file \& \-\-dumpi\-dfg Enable dumping DfgGraphs to .dot files at level \& \-\-dumpi\-graph Enable dumping V3Graphs to .dot files at level \& \-\-dumpi\-tree Enable dumping Ast .tree files at level \& \-\-dumpi\-tree\-json Enable dumping Ast .tree.json files at level \& \-\-dumpi\- Enable dumping everything in source file at level \& \-E Preprocess, but do not compile \& \-\-error\-limit Abort after this number of errors \& \-\-exe Link to create executable \& \-\-expand\-limit Set expand optimization limit \& \-F Parse arguments from a file, relatively \& \-f Parse arguments from a file \& \-FI Force include of a file \& \-\-flatten Force inlining of all modules, tasks and functions \& \-\-future0