UHD(1) User Commands UHD(1)

rfnoc_image_builder - Build UHD image using RFNoC blocks.

rfnoc_image_builder [-h] (-y YAML_CONFIG | -r GRC_CONFIG) [-C BASE_DIR] [-F FPGA_DIR] [-B BUILD_DIR] [-O BUILD_OUTPUT_DIR] [-E BUILD_IP_DIR] [-o IMAGE_CORE_OUTPUT] [-I INCLUDE_DIR] [-b GRC_BLOCKS] [-l LOG_LEVEL] [-R] [-G] [-W] [-S SECURE_CORE] [-K SECURE_KEY] [-d DEVICE] [-n IMAGE_CORE_NAME] [-t TARGET] [-g] [-Y] [--CHECK] [-s] [-P] [-j JOBS] [-c] [-p VIVADO_PATH] [-H] [-D] [--color {never,auto,always}]

show a help message and exit
Path to YAML configuration file (image core file). Either this option or --grc-config is required.
Path to .grc file to generate config from
Path to the base directory. Defaults to the current directory.
Path to directory for the FPGA source tree. Defaults to the FPGA source tree of the current repo.
Path to directory where the image core and and build artifacts will be generated. Defaults to "build-<image-core-name>" in the base directory.
Path to directory for final FPGA build outputs. Defaults to "build" in the base directory.
Path to directory for IP build artifacts. Defaults to "build-ip" in the base directory.
DEPRECATED! This has been replaced by --build-dir.
DEPRECATED! This option will be ignored.
Path to directory of the RFNoC Out-of-Tree module
Path to directory of GRC block descriptions (needed for --grc-config only)
Adjust log level
Reuse existing files (do not regenerate image core).
Just generate files without building the FPGA
Run build even when there are warnings in the build process.
Build a secure image core instead of a bitfile. This argument provides the name of the generated YAML.
Path to encryption key file to use for secure core.
Device to be programmed [x300, x310, e310, e320, n300, n310, n320, x410, x440]. Needs to be specified either here, or in the configuration file.
Name to use for the RFNoC image core. Defaults to name of the image core YML file, without the extension.
Build target (e.g. X310_HG, N320_XG, ...). Needs to be specified either here, on the configuration file.
Open Vivado GUI during the FPGA building process.
Stop the FPGA build process after Synthesis.
Run elaboration only to check HDL syntax.
Save Vivado project to disk.
Build only the required IPs.
Number of parallel jobs to use with make.
Cleans the IP before a new build.
Path to the base install for Xilinx Vivado if not in default location (e.g., /tools/Xilinx/Vivado).
Do not include source YAML hash in the generated source code.
Do not include date or time in the generated source code.
Enable colorful output. When set to 'auto' will only show color output in TTY environments (e.g., interactive shells).

This tool takes a YAML configuration file and generates an FPGA bitfile that can be used with an RFNoC-capable UHD device. The YAML configuration file describes the RFNoC blocks that are to be included in the FPGA image, along with the connections between the blocks, and any additional configuration that is required for the blocks.

UHD documentation: https://uhd.readthedocs.io/

Other UHD programs:

uhd_cal_tx_dc_offset(1) uhd_cal_rx_iq_balance(1) uhd_images_downloader(1) uhd_config_info(1) uhd_find_devices(1)

This manual page was written by Maitland Bottoms for the Debian project (but may be used by others).

Copyright (c) 2020 Ettus Research LLC

This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

December 2024 UHD 4