'\" t
.\"     Title: cxl-disable-bus
.\"    Author: [see the "AUTHOR(S)" section]
.\" Generator: Asciidoctor 2.0.20
.\"      Date: 2024-01-12
.\"    Manual: cxl Manual
.\"    Source: cxl
.\"  Language: English
.\"
.TH "CXL\-DISABLE\-BUS" "1" "2024-01-12" "cxl" "cxl Manual"
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.SH "NAME"
cxl-disable-bus \- Shutdown an entire tree of CXL devices
.SH "SYNOPSIS"
.sp
.nf
\fIcxl disable\-bus\fP <root0> [<root1>..<rootN>] [<options>]
.fi
.br
.sp
For test and debug scenarios, disable a CXL bus and any associated
memory devices from CXL.mem operations.
.SH "OPTIONS"
.sp
\-f, \-\-force
.RS 4
DANGEROUS: Override the safety measure that blocks attempts to disable a
bus if the tool determines a descendent memdev is in active usage.
Recall that CXL memory ranges might have been established by platform
firmware and disabling an active device is akin to force removing memory
from a running system.
.RE
.sp
\-\-debug
.RS 4
If the cxl tool was built with debug disabled, turn on debug
messages.
.RE
.SH "COPYRIGHT"
.sp
Copyright \(co 2016 \- 2022, Intel Corporation. License GPLv2: GNU GPL
version 2 \c
.URL "http://gnu.org/licenses/gpl.html" "" "."
This is free software:
you are free to change and redistribute it.  There is NO WARRANTY, to
the extent permitted by law.
.SH "SEE ALSO"
.sp
cxl\-disable\-port(1)