.TH "cpu_raw_data_t" 3 "libcpuid" \" -*- nroff -*- .ad l .nh .SH NAME cpu_raw_data_t \- Contains just the raw CPUID data\&. .SH SYNOPSIS .br .PP .PP \fR#include \fP .SS "Data Fields" .in +1c .ti -1c .RI "uint32_t \fBbasic_cpuid\fP [MAX_CPUID_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBext_cpuid\fP [MAX_EXT_CPUID_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBintel_fn4\fP [MAX_INTELFN4_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBintel_fn11\fP [MAX_INTELFN11_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBintel_fn12h\fP [MAX_INTELFN12H_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBintel_fn14h\fP [MAX_INTELFN14H_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBamd_fn8000001dh\fP [MAX_AMDFN8000001DH_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint32_t \fBamd_fn80000026h\fP [MAX_AMDFN80000026H_LEVEL][NUM_REGS]" .br .ti -1c .RI "uint64_t \fBarm_midr\fP" .br .ti -1c .RI "uint64_t \fBarm_mpidr\fP" .br .ti -1c .RI "uint64_t \fBarm_revidr\fP" .br .ti -1c .RI "uint32_t \fBarm_id_afr\fP [MAX_ARM_ID_AFR_REGS]" .br .ti -1c .RI "uint32_t \fBarm_id_dfr\fP [MAX_ARM_ID_DFR_REGS]" .br .ti -1c .RI "uint32_t \fBarm_id_isar\fP [MAX_ARM_ID_ISAR_REGS]" .br .ti -1c .RI "uint32_t \fBarm_id_mmfr\fP [MAX_ARM_ID_MMFR_REGS]" .br .ti -1c .RI "uint32_t \fBarm_id_pfr\fP [MAX_ARM_ID_PFR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64afr\fP [MAX_ARM_ID_AA64AFR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64dfr\fP [MAX_ARM_ID_AA64DFR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64isar\fP [MAX_ARM_ID_AA64ISAR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64mmfr\fP [MAX_ARM_ID_AA64MMFR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64pfr\fP [MAX_ARM_ID_AA64PFR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64smfr\fP [MAX_ARM_ID_AA64SMFR_REGS]" .br .ti -1c .RI "uint64_t \fBarm_id_aa64zfr\fP [MAX_ARM_ID_AA64ZFR_REGS]" .br .in -1c .SH "Detailed Description" .PP Contains just the raw CPUID data\&. This contains only the most basic CPU data, required to do identification and feature recognition\&. Every processor should be identifiable using this data only\&. .SH "Field Documentation" .PP .SS "uint32_t cpu_raw_data_t::amd_fn8000001dh[MAX_AMDFN8000001DH_LEVEL][NUM_REGS]" when the CPU is AMD and supports leaf 8000001Dh (topology information for the DC) this stores the result of CPUID with eax = 8000001Dh and ecx = 0, 1, 2\&.\&.\&. .SS "uint32_t cpu_raw_data_t::amd_fn80000026h[MAX_AMDFN80000026H_LEVEL][NUM_REGS]" when the CPU is AMD and supports leaf 80000026h (Extended CPU Topology leaf) this stores the result of CPUID with eax = 80000026h and ecx = 0, 1, 2\&.\&.\&. .SS "uint64_t cpu_raw_data_t::arm_id_aa64afr[MAX_ARM_ID_AA64AFR_REGS]" when then CPU is ARM-based and supports ID_AA64AFR* (AArch64 Auxiliary Feature Register) .SS "uint64_t cpu_raw_data_t::arm_id_aa64dfr[MAX_ARM_ID_AA64DFR_REGS]" when then CPU is ARM-based and supports ID_AA64DFR* (AArch64 Debug Feature Register) .SS "uint64_t cpu_raw_data_t::arm_id_aa64isar[MAX_ARM_ID_AA64ISAR_REGS]" when then CPU is ARM-based and supports D_AA64ISAR* (AArch64 Instruction Set Attribute Register) .SS "uint64_t cpu_raw_data_t::arm_id_aa64mmfr[MAX_ARM_ID_AA64MMFR_REGS]" when then CPU is ARM-based and supports ID_AA64MMFR* (AArch64 Memory Model Feature Register) .SS "uint64_t cpu_raw_data_t::arm_id_aa64pfr[MAX_ARM_ID_AA64PFR_REGS]" when then CPU is ARM-based and supports ID_AA64PFR* (AArch64 Processor Feature Register) .SS "uint64_t cpu_raw_data_t::arm_id_aa64smfr[MAX_ARM_ID_AA64SMFR_REGS]" when then CPU is ARM-based and supports ID_AA64SMFR* (AArch64 SME Feature ID Register ) .SS "uint64_t cpu_raw_data_t::arm_id_aa64zfr[MAX_ARM_ID_AA64ZFR_REGS]" when then CPU is ARM-based and supports ID_AA64ZFR* (SVE Feature ID register) .SS "uint32_t cpu_raw_data_t::arm_id_afr[MAX_ARM_ID_AFR_REGS]" when then CPU is ARM-based and supports ID_AFR* (AArch32 Auxiliary Feature Register) .SS "uint32_t cpu_raw_data_t::arm_id_dfr[MAX_ARM_ID_DFR_REGS]" when then CPU is ARM-based and supports ID_DFR* (AArch32 Debug Feature Register) .SS "uint32_t cpu_raw_data_t::arm_id_isar[MAX_ARM_ID_ISAR_REGS]" when then CPU is ARM-based and supports D_ISAR* (AArch32 Instruction Set Attribute Register) .SS "uint32_t cpu_raw_data_t::arm_id_mmfr[MAX_ARM_ID_MMFR_REGS]" when then CPU is ARM-based and supports ID_MMFR* (AArch32 Memory Model Feature Register) .SS "uint32_t cpu_raw_data_t::arm_id_pfr[MAX_ARM_ID_PFR_REGS]" when then CPU is ARM-based and supports ID_PFR* (AArch32 Processor Feature Register) .SS "uint64_t cpu_raw_data_t::arm_midr" when then CPU is ARM-based and supports MIDR (Main ID Register) .SS "uint64_t cpu_raw_data_t::arm_mpidr" when then CPU is ARM-based and supports MPIDR (Multiprocessor Affinity Register) .SS "uint64_t cpu_raw_data_t::arm_revidr" when then CPU is ARM-based and supports REVIDR (Revision ID Register) .SS "uint32_t cpu_raw_data_t::basic_cpuid[MAX_CPUID_LEVEL][NUM_REGS]" contains results of CPUID for eax = 0, 1, \&.\&.\&. .SS "uint32_t cpu_raw_data_t::ext_cpuid[MAX_EXT_CPUID_LEVEL][NUM_REGS]" contains results of CPUID for eax = 0x80000000, 0x80000001, \&.\&.\&. .SS "uint32_t cpu_raw_data_t::intel_fn11[MAX_INTELFN11_LEVEL][NUM_REGS]" when the CPU is intel and it supports leaf 0Bh (Extended Topology enumeration leaf), this stores the result of CPUID with eax = 11 and ecx = 0, 1, 2\&.\&.\&. .SS "uint32_t cpu_raw_data_t::intel_fn12h[MAX_INTELFN12H_LEVEL][NUM_REGS]" when the CPU is intel and supports leaf 12h (SGX enumeration leaf), this stores the result of CPUID with eax = 0x12 and ecx = 0, 1, 2\&.\&.\&. .SS "uint32_t cpu_raw_data_t::intel_fn14h[MAX_INTELFN14H_LEVEL][NUM_REGS]" when the CPU is intel and supports leaf 14h (Intel Processor Trace capabilities leaf)\&. this stores the result of CPUID with eax = 0x12 and ecx = 0, 1, 2\&.\&.\&. .SS "uint32_t cpu_raw_data_t::intel_fn4[MAX_INTELFN4_LEVEL][NUM_REGS]" when the CPU is intel and it supports deterministic cache information: this contains the results of CPUID for eax = 4 and ecx = 0, 1, \&.\&.\&. .SH "Author" .PP Generated automatically by Doxygen for libcpuid from the source code\&.